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Espressif Systems /ESP32-S3 /RTC_CNTL /WDTCONFIG0

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Interpret as WDTCONFIG0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WDT_CHIP_RESET_WIDTH 0 (WDT_CHIP_RESET_EN)WDT_CHIP_RESET_EN 0 (WDT_PAUSE_IN_SLP)WDT_PAUSE_IN_SLP 0 (WDT_APPCPU_RESET_EN)WDT_APPCPU_RESET_EN 0 (WDT_PROCPU_RESET_EN)WDT_PROCPU_RESET_EN 0 (WDT_FLASHBOOT_MOD_EN)WDT_FLASHBOOT_MOD_EN 0WDT_SYS_RESET_LENGTH 0WDT_CPU_RESET_LENGTH 0WDT_STG3 0WDT_STG2 0WDT_STG1 0WDT_STG0 0 (WDT_EN)WDT_EN

Description

configure rtc watch dog

Fields

WDT_CHIP_RESET_WIDTH

chip reset siginal pulse width
WDT_CHIP_RESET_EN

wdt reset whole chip enable
WDT_PAUSE_IN_SLP

pause WDT in sleep
WDT_APPCPU_RESET_EN

enable WDT reset APP CPU
WDT_PROCPU_RESET_EN

enable WDT reset PRO CPU
WDT_FLASHBOOT_MOD_EN

enable WDT in flash boot
WDT_SYS_RESET_LENGTH

system reset counter length
WDT_CPU_RESET_LENGTH

CPU reset counter length
WDT_STG3

1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en
WDT_STG2

1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en
WDT_STG1

1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en
WDT_STG0

1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en
WDT_EN

enable rtc watch dog

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data